Compact thermal models for thermally aware design of VLSI circuits

During the last two decades, self-heating has become a significant bottleneck to the continued scaling of microelectronics. This is a particular problem in emerging finFET designs because of the use of thick buried oxide layers which impede heat flow to the heat sink. A possible solution is to use architectural and circuit-level techniques to make the temperature field as uniform as possible on the chip. These techniques require a prediction of temperature at the level of 100s-1000s of transistors, and must relate the predicted temperature to the activity level of the devices. In this paper, compact thermal models of circuit components are developed for use in cell-level electrical models of VLSI circuits, and ultimately for thermally-aware component placement and optimization. Fourier theory is used to model NAND and NOR gates and inverters employing finFETs at the 28 nm node. Electron-phonon scattering sources are computed using the drift-diffusion solver TAURUS. Compact models are then developed from the thermal simulation and used in cell-level representations of typical circuits to make thermal predictions on the scale of 100's of transistors. The technique is readily scaled up recursively to larger and larger scales and represents a viable methodology for multiscale simulation of microelectronics