A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

This paper describes the design and realization of a 15-bit 30-MS/s three-step ADC for imaging applications with a peak-to-peak signal to rms noise ratio (DR
_pp
) of 85 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single-poly, 0.18-mum CMOS, measures 1.4 mm
²
, and dissipates 145 mW from 1.8-V and 3.3-V supplies