Sensitivity Design of the Chip-in-Substrate Package Using DOE with Factorial Analysis Technology

As electronic devices become more complicated and the need for semiconductor chips in portable products increases, the demand for smaller and lighter chips and packages becomes greater. However, because of the different temperature loading from the manufacturing process, the mismatch in the coefficient of thermal expansion (CTE) between different materials affects the packaging reliability. In this study, the Chip-in-Substrate Package (CiSP), which has been developed by ITRI/ERSO and Fraunhofer IZM, is chosen as the test instrument. For the purpose of comprehending the stress/strain accumulation during the manufacturing process, a process modeling methodology has been executed to determine the evolution of stresses distribution during the sequential fabrication of CiSP structures. In addition, to further improve the packaging design of CiSP, the stress/strain variation around the most critical region is investigated by means of the design of experiment (DOE). A two-step design method based on the validated model is proposed for the development of the CiSP. The analytic results reveal that decreasing the thickness of the lamination layer and increasing the thickness of the interconnect can effectively reduce the stress concentration phenomenon. The robust design parameters for the CiSP could be achieved through the analytical procedures presented in this study. Therefore, the CiSP can be fabricated within the validated design parameters and can consequently meet the demand of decreasing the amount of time involved in product development.