Current bias testing of differential circuits

It is noted that differential circuits are prone to a class of faults that reduce the signal between the two outputs without causing a stuck fault or delay. The authors examine the addition of test bias circuits to aid testing of these faults. In particular, the application of current biasing to memory circuits is considered. It is shown that the main benefit of biasing application is the detection of defects that reduce noise margin. Other substantial benefits are transforming some delay defects into stuck-at faults, greatly increasing the product quality, and reducing the need for an expensive high-performance test.<
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