A 64 bit CMOS mainframe execution unit macrocell with error detecting circuit

A 64-bit CMOS mainframe execution unit macrocell with error detecting circuits is proposed. It adopts a parity predicting logic structure in order to reduce the number of circuit stages in the ALU (arithmetic and logic unit) critical path. By utilizing this structure, a one-bit-error detecting function is integrated. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. Through the use of these techniques, 30% faster operation is achieved.<
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