Performance and technology trade-offs of BiCMOS submicron processes for ASIC applications

The technology trade-offs of various BiCMOS processes of submicron feature size are discussed. A method of quantifying performance, cost, density, and reliability is presented. The authors discuss the cost trade-offs and give a comprehensive performance analysis of the high-end and low-end BiCMOS processes at the 0.8- mu m feature size. It is shown that a 2* performance improvement of BiCMOS over CMOS, as predicted in the literature, is not realistic for performance optimized circuits.<
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