SW-HW Co-design and Fault Tolerant Implementation for the LRID Wireless Communication System

This paper presents the development of a wireless communication system, the RF Identification Tag, built and tested in Heriot-Watt University, Edinburgh. The design flow commences in SPIN, a high level modelchecking tool at present deployed towards the verification of safety critical software designs including NASA missions. The formally verified model of the application is then enhanced with software based monitoring architectures comparable with that applied in conventional firmware development such as the watchdog timer defending rational control related execution of the high level system representation. Following automated synthesis into hardware (HDL) with the aid of an ESL method, the generated RTL design can be further protected against increased levels of radiation and SEUs with the aid of the xTMR tool. It is claimed that a development route of this type promotes high levels of algorithmic testability and reliability attained via fault prevention means in the model checking process as well as multi-layered runtime monitoring and fault management strategies leveraging upon the design on the vertical implementation phase. The application developed in the proposed lifecycle and targeting the FPGA technology is finally tested under a lab emulated EMI scheme and system survivability is examined and quantified. Reliability is then estimated and analyzed in the CASRE tool (developed by JPL NASA).