Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration

With the high complexity of future System- on- Chips, many aspects such as synchronization, system control and system test and validation will be difficult to manage. Clock signals stretching over the complete die will suffer from delays and cause synchronization problems, a centralized system control will become a bottle neck and the high number of system components will cause further problems when verifying the system functional correctness. Self- adaptive systems are an important field of research in order to find solutions to these problems. In this paper, a concept for self- recovery from behavioural failures is presented. The proposed methods are based on earlier work in this area which exploits dynamic and partial hardware reconfiguration. Hardware reconfiguration is an important feature in self- adaptive systems since it offers a higher degree of freedom, and in this case it also offers the possibility for a system to recover from a failure during run-time.