A Low Power, High SFDR, ROM-Less Direct Digital Frequency Synthesizer

This paper describes the design of a ROM-Less Direct Digital Frequency Synthesizer. The Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is -91.5ldBc. A DDFS IC has been designed in HP 0.5μm standard N-Well CMOS process technology, and that's layout has 2.489mm
²
area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz.