A doughnut layout style for improved switching speed with CMOS VLSI gates

A doughnut style for physical layout of CMOS gates which improves the switching speed of the gates compared to a standard layout style is discussed. This improvement in performance is obtained by decreasing the self-loading output capacitance for a given W/L ratio of the transistor channels. A design for a 30-bit incrementer which was fabricated and tested as a 3- mu m VLSI circuit is included as an example of an application for the doughnut-style gates. The incrementer has a propagation delay of less than 10 ns through nine stages of logic gates with large fan-outs at three of the stages.<
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