A 32 K ASIC synchronous RAM using a two-transistor basic cell

A 32 K synchronous RAM using a two-transistor basic cell has been developed for use with a 100 K compact gate array. The basic cell consists of only two transfer gates and a storage capacitor and thus results in a very dense memory array. The RAM operates as a static RAM during system operations and provides both serial and parallel data ports. It can be reconfigured into 1 K*32, 2 K*16, 4 K*8, etc. depending on the system needs. An access time of 40 ns was achieved for a test chip at an operating power of 175 mW.<
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