An investigation on the cutoff characteristics of sub-quarter-micron SOI MOSFET

The influence of DIBL on the latch condition for subquarter-micron SOI (silicon-on-insulator) MOSFETs is investigated. It is found that the main effect of DIBL is lowering the minimum hole current for latch. Simulated results on device structures proposed to improve cutoff characteristics are also shown. The cutoff characteristics of an SOI MOSFET (L=0.2 mu m) for which higher acceptor concentration (Na=2*10/sup 17/ cm/sup -3/) SOI film and LDD (lightly doped drain) structure are adopted are shown. These design options are effective for reducing DIBL at the SOI bottom.<
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