A 0.5 mu m CMOS/SOI technology

The authors describe a 0.5- mu m fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5- mu m CMOS/SOI technology has been developed for SRAM and logic applications. The circuit performance is improved by 40% over an equivalent bulk CMOS as the result of the lightly doped substrate and fully depleted CMOS device design. Using a fully depleted FET design on thin SOI film can eliminate the 'kink effect' and anomalous subthreshold current caused by the floating substrate. The devices are fabricated on p-type SIMOX wafers with a thickness of 100 nm and a background doping level of approximately 1*10/sup 15/. The I-V characteristics of the n- and p-MOSFETs are shown.<
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