Delay macro modeling of CMOS gates using modified logical effort technique

Modified logical effort (MLE) technique is proposed in this paper to provide delay estimation for CMOS gates. The model accounts for the behavior of series connected MOSFET structure (SCMS), the switching input transition time and internodal charges. Also the model takes into account deep submicron effects such as mobility degradation and velocity saturation. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model. An average error of 3.1% was obtained based on UMC's 0.13/spl mu/m technology.