An FPGA implementation of a structured irregular LDPC decoder

In this paper, a code construction method of irregular low-density parity-check (LDPC) codes is presented, which facilitates the hardware implementation of belief propagation (BP) decoders and leads to low error floors as well. To verify the effectiveness of this construction, an FPGA-based decoder is designed and implemented, where a novel non-uniform quantization scheme for BP decoding is used, so that the performance loss compared to infinite-precision decoding is less than 0.1 dB. The decoding throughput of the decoder can reach as high as 50 Mbps.