A 1.4 V/5 GHz, 90-nm system-in-a-package LNA

We describe a SiP LNA implemented in a 90-nm CMOS technology with a package based micro-strip matching network. We present device and micro-strip co-optimization techniques that achieve a better than -10 dB match over a 600 MHz bandwidth around 5.2 GHz with a peak s/sub 11/ of /spl ap/ -30 dB and a noise figure of 1.9 dB while consuming 15 mA from a 1.4 V supply. An LNA desensitization technique is described that alleviates mismatch errors typically associated with low-cost package materials. The off-chip input matching network is suitable for multi standard optimization and is an efficient alternative to on-chip matching for high volume manufacturing.