An instruction-level analytical power model for designing the low power systems on a chip

In this paper, an instruction-level analytical power model for the low power systems on a chip (SoC) is proposed. The inter-instruction effects are obtained with combining different instructions for program running in a processor, such as DSP, CPU for embedded SoC. Variations in base costs as different operands and addresses are also observed. Finally, power consumption of one section of DSP program is measured and compared with the estimated value by our model, which shows that the proposed model is simple and effective for estimating the power consumption of program and it is useful for further software/hardware co-design of SoC.