A way of enhancing test quality and restraining the increase of test cost for deep sub-micron integrated circuits

Enhancing test quality and restraining test cost are two main topics in the domain of test and design for testability of deep sub-micron integrated circuits. This paper presents a multi-fault oriented test and DFT resolution scheme for DSM IC. The scheme can enhance the test quality of deep sub-micron chips by using a test suite consisted of stuck-at fault test, delay fault test and delta-IDDQ test. And it can restrain the increase of test cost by adopting a special ATPG strategy to reduce scan-based stuck-at test patterns. A design paradigm of 0.18 mum MCU to which the scheme is applied is also introduced in the paper