Reconfigurable VLSI architecture for VBSME in MPEG-4 AVC/H.264

VBSME is adopted in the MPEG-4 AVC/H.264 standard. In this paper, we proposed a new reconfigurable VLSI architecture for VBSME with 3 levels of computing complexity to support FS and fast search area sub-sampling ME algorithms. The architecture can reuse the smaller blocks' SADs to calculate 41 motion vectors of a 16times16 block in parallel. Our design was implemented with 0.25mum CMOS technology. Under a clock frequency of 52Mhz, the architecture allows the real-time processing of 352times288 (or 720times576) at 30fps with FS (or fast algorithms) in a search range [-16, +15]