Low-power FIR filter based on standard cell

In recent years, power consumption along with silicon area has become the key factor in the chip design, especially in the digital signal processing block. Most of digital signal processing block are designed in standard cell. One way of low power design based on standard cell is using minimum-sized device. This paper presents a low-power scheme for the VLSI implementation of finite-impulse response (FIR) filters based on standard cell. The scheme is a cross level solution in the view of design flow. A multi-hierarchy pipeline scheme is in the architecture level. Integrating addition into Wallace/spl I.bar/tree is used in logic level, which guarantees achieving minimum-sized device solution in circuit level. Simulation shows that 20% of the power is saved with the proposed scheme.