A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS

An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90 nm digital CMOS technology is presented. The circuit consisting of low noise amplifier, transconductance amplifier and switching mixer, offers 32.5 dB dynamic range with digitally-configurable voltage gain of 40 dB down to 7.5 dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly-linear second-order low-pass filtering to reject close-in interferers. The front-end gains can be configured with an automatic-gain-control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and +50 dBm IIP/sub 2/ at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 mm/sup 2/. The LNA, TA and mixer consume less than 15.3 mA at a supply voltage of 1.4 V.