Report on the formal specification and partial verification of the VIPER microprocessor

VIPER (verifiable integrated processor for enhanced reliability) is a 32-b microprocessor architecture. The claim that the gate level of the VIPER microprocessor is mathematically verified is examined. Although a great deal of effort has been expended on the formal specification and verification of VIPER, there is not sufficient evidence to substantiate the claim that the VIPER gate-level specification (the implementation netlist) has been proven to implement its top-level specification (the instruction interpreter). Some of the broader issues in managing formal hardware verification projects are discussed, using the VIPER projects as an example. The specification and verification approach used for VIPER is also contrasted with that used during the specification and verification of the FM8502 microprocessor.<
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