Intrinsic limitations on the performance and reliability of high-k gate dielectrics for advanced silicon devices

This paper is based on a tutorial/contributed paper pairing that addresses intrinsic limitations for the substitution of high-k gate dielectrics for SiO
₂
and Si oxynitride alloys in order to extend the scaling of complementary metal oxide semiconductor (CMOS) integrated circuits and systems for at least another 15 to 20 years. An understanding of the intrinsic limitations of the these proposed alternative high-k dielectrics is developed in a systematic way by first addressing the electronic structure differences of these alternative dielectrics with respect to SiO
₂
and Si oxynitride alloys, and then addressing the issues related to the entire gate stack including: i) interfaces with Si substrate; ii) the gate electrode; and iii) internal dielectric interfaces between the high-k dielectric and interfacial layers, e.g., nitride SiO
₂
at the Si interface