Integration of a double polysilicon, fully self-aligned bipolar transistor into a 0.5 mu m BiCMOS technology for fast 4 MBit SRAMs

The single polysilicon, non-self-aligned bipolar transistor in a 0.5- mu m BiCMOS technology has been converted to a double polysilicon, fully self-aligned bipolar device with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density SRAM circuits.<
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