Computational study of carbon nanotube p-i-n tunnel FETs

Reducing transistor leakage current by increasing the sub-threshold slope beyond the thermal limit (60mV/decade at room temperature) could alleviate the heat dissipation requirements of high-density ICs. This paper examines the potential of a carbon nanotube p-i-n tunnel FET for less than 60mV/dec operation. Both ballistic transport and transport with inelastic scattering are considered. The device performance is compared to that of a carbon nanotube n-i-n MOSFET. An extensive discussion on device optimization for p-i-n tunnel FETs is also presented