A low phase noise 2 GHz VCO using 0.13 /spl mu/m CMOS process

A 2 GHz LC VCO with a large improvement in phase noise is designed and implemented in 0.13/spl mu/m CMOS process. It has phase noise of -100.7 dBc/Hz, -130.6 dBc/Hz, and -140.8 dBc/Hz at 100 kHz, 1 MHz, and 3 MHz offset frequencies from the carrier, respectively. The phase noise reduction of about 10 dB is observed for all controllable voltage range, as compared with a comparable conventional VCO. This VCO consumes 3.29 mA from a 1.8 V supply with the silicon area of 500 /spl mu/m /spl times/ 850 /spl mu/m.