Pre-decoding mechanism for superscalar architecture

A predecoding mechanism for superscalar processors that is necessary to issue instructions to plural functional units is described. Using a predecoding mechanism, a processor can issue instructions without increasing the cycle time or the branch penalty. The predecoder decides which functional unit should execute an instruction during a cache miss and refill. A special tag, the call predecode tag, is generated by the predecoder. This tag is saved with instructions to an instruction cache memory. The processor fetches instructions with the predecode tag and issues instructions controlled by the predecode tag. Using this mechanism, fast cycle times, comparable to those of RISC processors, are attained.<
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