A Reconfigurable Fabric and Associated CAD Algorithms for Multirate LDPC Decoding

We present the design of a reconfigurable VLSI architecture suitable for multirate LDPC decoding. The basic decoder fabric is a square matrix of processing elements which communicate with each other through an interconnection network. The interconnection network consists of links and switches. The connectivity between processing elements is completely defined by scheduling the interconnection network; we describe a CAD algorithm for computing efficient schedules