A low-power analog motion estimation processor for digital video coding

Analog circuit techniques can be beneficially applied to reduce the circuit complexity and power consumption of motion estimation processors for digital video encoding. However, analog circuits are sensitive to mismatch which affects motion estimation. This paper presents the design of an analog motion estimation processor which overcomes these limitations. A novel architecture is described featuring pixel reuse and input offset error cancellation. The proof-of-concept realization was fabricated in 0.8-/spl mu/m CMOS, and operates on 4/spl times/4 pixel blocks and a search area of 8/spl times/8 pixels. However, the architecture is scalable to larger block sizes and more advanced technologies. Measured results for various QCIF video sequences at 15-f/s showed excellent PSNR performance. The prototype dissipates 0.9 mW of power from a single 3-V power supply and occupies an area of 0.95 mm/sup 2/. Energy consumption is 1.51 nJ per motion vector.