Optimized multipliers for large unsigned integers

Modern FPGAs come now with a significant number of on-chip n-bit/spl times/n-bit multipliers, which would help designers to efficiently implement multiplication-intensive applications. However, when these applications require multiplying operands with a size exceeding n-bits, then one needs to solve the problem of how to efficiently carry out the multiplication operation. As a possible solution, one can use a divide-and-conquer strategy. This strategy transforms the multiplication into multiplications for operands with no more than n bits, followed by a set of addition operations. While these multiplications can now be performed efficiently using n-bit/spl times/n-bit multipliers, the questions are how to decrease the number of addition operations and how to achieve more optimized realizations. This paper proposes a new approach for solving these questions, and demonstrates its effectiveness through realization of multipliers with operands ranging from 19 bits to 68 bits using Xilinx Spartan-3 FPGAs. Compared to multipliers produced by synthesis tools, experimental results show that the proposed approach can, on average, improve the speed by 6.2%, and the area by 2.9% in terms of slices and by 2% in terms of look up tables. Significant improvements are noticed when compared to results obtained from Xilinx' IP CORE Generator.