Asynchronous architectures for nanometer scales

Summary form only given. The ongoing developments in nanotechnology promise extremely powerful computers, but they may require new designs. Heat dissipation will become a major issue at the high integration densities allowed by nanotechnology, and it is therefore unsurprising that techniques to reduce it, like asynchronous timing, have attracted growing interest in recent years. At the same time, some researchers have come to realize that the types of signal and circuit realizable by nanotechnology may be very different from those in solid-state electronics. Signals, for example, may be encoded by particles, giving them a token-like nature. Primitive operators in circuits will have to be designed with this in mind, and asynchronous circuits are no exception to this. Ease of manufacturing is another important issue for nanocomputer designs. A regular structure tends to facilitate bottom-up manufacturing techniques like directed molecular self-assembly. Cellular automata are obvious candidates in this context. Though asynchronous cellular automata have been investigated for years, the methods to compute on them have been limited to simulating synchronous cellular automata on them. As this requires that all cells are busy most of the time with ensuring that they run approximately in lock-step with each other, this method is unlikely to reduce power consumption of the cells in physical implementations, defeating the use of asynchronous timing in the first place. This presentation shows an alternative, in which only cells in the neighbourhood of signals are active while the others are quiescent. This method is based on the embedding of delay-insensitive circuits on asynchronous cellular automata.