Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips

Early performance estimation of a system-on-chip design is a key issue for a successful design methodology. One of the most important parameters is the run time of a function. Especially optimization techniques like hw/sw partitioning rely on those estimations. This paper presents a static analysis method in order to characterize a hardware acceleration unit regarding its run time. The performance of the presented method is shown on several examples from the embedded systems area and compared to results from high level synthesis.