Multiplierless Reconfigurable Processing Element And Its Applications to DSP Kernels

This paper proposes a new reconfigurable arithmetic architecture for DSP kernels. This architecture can perform function of MAC operation based on distributed arithmetic without multiplier. Because of multiplierless characteristic, it can say that the proposed architecture have less complexity and smaller area. The proposed architecture is also based on 1-bit functional unit which performs logical operations, addition, subtraction, and shift and it can do configuration of 4/8/16 bit unit. Therefore it has high flexibility and small overhead. We apply various algorithms of DSP kernels such as multiplication of matrix, FIR filter, 2-D DCT and motion estimation.