System-level modeling and validation increase design productivity and save errors

As the complexity of system on chip (SoC) devices rises to include scores, in some cases hundreds, of distinct blocks, system validation becomes a critical concern. A variety of techniques have emerged to help designers verify that individual blocks of a device meet performance specification. But what about functional intent? Are performance goals achieved? In this paper, we make the case for high-level system validation before RTL implementation, and present a flow to approach this increasingly essential task.