A new approach for real-time histogram equalization using FPGA

This paper presents a novel design for real-time histogram equalization based on field programmable gate arrays (FPGAs). The design is implemented using non-conventional schemes to compute the histogram statistics and equalization in parallel. Counters are used in conjunction with a dedicated decoder specially designed for this purpose. The hardware is fast, simple, and flexible with reasonable development cost. The proposed system is implemented using Stratix II family chip type EP2S15F484C3. The maximum clock frequency can reach up to 250 MHz. In this case, the total time required to perform histogram equalization for an image of size 256 /spl times/ 256 is 0.262 ms.