Global-routing driven placement strategy in analog VLSI physical designs

The potential problems of the conventionally separate placement and global routing cannot be negligible for the analog integrated circuits, which often involve complex constraints. This paper presents a novel two-stage placement technique to solve the analog macro-cell placement problem. The entire placement procedure is divided into global placement and detailed placement stages. During the global placement, a hybrid genetic placement approach using a half-perimeter wire-length estimator is employed. It performs a rough but quick search to locate the region of the optimum. In the detailed placement, a very fast simulated re-annealing placement approach and a minimum-Steiner-tree based global routing are executed simultaneously. In this way, the optimum can be found by searching relatively small region. The experiments show the proposed algorithm can generate higher quality layouts than the conventional approaches.