Integrated optical nanoprobe sensor implemented using a mixed technology CMOS fabrication process

It has been shown that a sub-wavelength nanoprobe (consisting of a sharpened optical fiber with a nanoscale optical aperture) can be used to produce microscopy images with spatial resolutions smaller than the optical wavelength. While these optical devices have been available for a decade, there use in near field scanning optical microscopy (NSOM) systems is limited by the nonuniformity of the probe fabrication process, and the complexity of the signal processing and control electronics. Recently, a new MEMS based probe fabrication process was developed that enables the production of nanoprobes with uniform and repeatable physical and optical characteristics. In this paper we investigate the possibility of integrating a nanoprobe with a CMOS based signal processing circuitry. When coupled with the new optical nanoprobes, this technology could potentially be used in the design and implementation of a compact NSOM system and thus enable the cost effective introduction of NSOM technology into a new set of applications including biomedical imaging and ultra high density data storage. Fabricated using an AMI 1.5 /spl mu/m CMOS process, the core of this project involves the design and fabrication of a CMOS chip that includes four different CMOS photoreceiver circuits V-grooves which are fabricated using a MEMS based post process etching step. The V-grooves are used for passive alignment of optical nanoprobes with the on-chip CMOS based photodetectors which are realized using the N-well/P-substrate junction. This photodiode has been used in all four types of the photoreceiver circuits in order to accommodate nW optical input signals. Based on recent development of CMOS photosensor technology, two types of active pixel and two types of passive pixel circuits have been designed. All four circuits are based on charging/discharging a capacitor to perform integration of the photogenerated current. If the integration process is linear and charging/discharging current I is a constant a simple relationship of /spl Delta/V//spl Delta/t = I/C should be satisfied. For maximum possible /spl Delta/V of 5 volts, there exists a maximum allowable sampling period for specific value of the charging/discharging current and integration capacitor. Unfortunately, in each circuit the value of charging/discharging current and total capacitance including parasitic capacitances are hard to determine. According to the T-SPICE simulation, a comparison of maximum allowable sampling period vs. photocurrent for four different photoreceiver circuits laid out is presented. Photoreceiver circuit evaluation and comparison have also done experimentally by using both the packaged and unpackaged die. Following the experimental confirmation that the photoreceiver circuits function as designed, the unpackaged die is post processed to produce the V-groove structures, and circuit evaluations are again done to access any performance degradation resulting from the post processing step. Finally, nanoprobes are attached into the V-grooves and the performance of the integrated optical nanoprobe with CMOS photoreceiver circuitry is evaluated.