An 8-b 20-Msample/s pipelined A/D converter in 0.5-/spl mu/m CMOS with 7.8 ENOB

This paper presents an 8-b 20-Msample/s pipelined analog-to-digital converter (ADC) designed in 0.5-/spl mu/m CMOS technology. On first silicon this converter achieved 7.8 effective-number-of-bits (ENOB), a peak differential-non-linearity (DNL) of -0.36LSB and integral-non-linearity (INL) of 0.35LSB.