Dark address event representation imager

A hybrid dark-active address-event representation (AER) imager has been designed, simulated and laid out in a commercially available 0.5 /spl mu/m CMOS process. The imager comprises a 16 /spl times/ 16 array of tunable active pixels each of which is approximately 33 /spl times/ 30 /spl mu/m/sup 2/ in area, with a 19% fill factor. It operates both in: (1) an imaging mode; and (2) a "dark" AER mode wherein the individual pixels asynchronously generate voltage pulses, or spikes, when the incident light on a pixel falls below a user defined threshold. In the dark AER mode, individual pixels sense whether they are occluded (dark), or not, by integrating the difference between the photocurrent and a tunable bias current onto the photodiode junction capacitance. Charge accumulates on an occluded photodiode because the photocurrent is smaller than the bias current. The capacitor voltage is then buffered by a source follower and, for a dark photodiode, increases until it crosses the threshold of a CMOS inverter, whereupon it is converted into a logic "high" event. As these dark digital events arise, their row and column addresses are priority encoded in real-time and then multiplexed together for serial readout. Simulations indicate that events are reliably generated at 1 ms and that data readout rates can operate efficiently several orders of magnitude faster.