A low power, high SFDR, ROM-less direct digital frequency synthesizer

This paper describes the design of a ROM-less direct digital frequency synthesizer. The spurious free dynamic range (SFDR) of the proposed DDFS system is -91.51dBc. A DDFS IC has been designed in HP 0.5/spl mu/m standard N-Well CMOS process technology, and that's layout has 2.489mm/sup 2/ area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz.