Study of 90-nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

We report 90-nm MOSFET subthreshold hump characteristics obtained for the first time by using a newly developed MOSFET array test structure. The array contains small-scale device-under-test groups with a new poly-Si gate layout pattern, which eliminates the influence of gate leakage and off leakage currents observed on measured MOSFET parameter data such as Vth, Ion, and subthreshold slope. We confirmed that subthreshold humps occur at random in an array. The rate at which humps occur is expressed as a percentage with respect to the whole array (referred to as the hump occurrence rate); the rate depends on chips from a wafer. It is also confirmed that the influence of subthreshold humps on /spl sigma/(Vth) is not negligible, and we revealed that it is important to design RF/analog circuits with an appropriate current density to reduce their influence. By extracting hump variations using a MOSFET array, it is possible to accurately estimate and reduce the standby current in logic large-scale integration (LSI) chips.