A stacked-CMOS cell technology for high-density SRAM's

A stacked-CMOS SRAM cell technology for high-density SRAMs has been developed. It has been found that the increase of the on-current of the thin-film transistor (TFT) load leads not only to the increase of the cell noise margin, but also to the reduction of the cell area. The improvement of the electrical characteristics of the TFT load has been achieved by enlarging the grains of the polysilicon film through the use of a novel solid-phase growth technique. As a result, TFT loads with on/off current ratio of 10/sup 5/ and off-current of 0.07 pA/ mu m, both promising for high-density SRAMs, have been obtained.<
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