3D simulation of parasitic MOSFET effects for box isolation technologies

Despite the higher integration capability, trench isolation in MOS technologies presents a number of problems associated with the fabrication of deep trenches as well as problems arising from the electrical properties of the parasitic MOSFETs formed in conjunction with the trenches. The latter problem is addressed. The 3-D device simulator SECOND was used to quantify the contribution of both the lateral and vertical parasitic MOSFETs as a function of channel and well doping, trench width, and bias conditions. The I-V characteristics of all three MOSFETs as a function of technology parameters, are discussed along with derivation of design rules for box isolation technologies.