A Functional-Level Test Generation Methodology Using Two-Level Representations

This paper proposes the use of a functional-level testing methodology based on the generation of test vectors from the functional descriptions of combinational circuits under test. The approach that is adopted involves the generation of a two-level AND-OR, or OR-AND implementation from a circuit's functional description, the generation of test vectors by way of a PODEM based algorithm for the two-level implementation, and the application of the generated tests on a specific implementation(s) of the circuit under test. This approach is experimentally evaluated on various combinational circuits, and is shown to be successful in achieving very high fault-coverages without relying on implementation details of the circuits that are tested.