Tutorial/Panel Languages for Behavioral Description and Synthesis

This session begins with an introduction to the new behavioral design language standard under development in Japan. Following this half hour tutorial a discussion addresses the question of whether a single standard, such as VHDL, is sufficient for all tasks associated with the design, verification, and synthesis, of electronic systems. Each of the panelists will address the language standard activity from their own perspective and with an emphasis on the use of standard behavioral languages for the unambiguous specification and description of digital systems. In particular, efforts in Japan and Europe to establish standard behavioral description languages will be contrasted with the VHDL effort on-going in the United States.