Technology and circuit design considerations in quasi-planar double-gate SRAM

SRAM is likely to remain the largest, leakiest, and most process-sensitive circuit block on chip. FinFET, a width-quantized, quasi-planar, double-gate technology, has emerged as the most likely candidate to replace classical technologies around the 45-nm node. This paper studies the impact of FinFET design choices on device and SRAM circuit metrics to understand how its unique properties can be suitably harnessed. Width-quantization limits SRAM sizing choices, while quasi-planarity allows increased cell current by increasing fin height. Conversely, the latter property can be exploited to increase V/sub t/ and/or decrease V/sub dd/ to achieve exponential leakage savings at constant area and read access time. We explore both approaches to selecting the right combination of device structure, V/sub t/ and V/sub dd/ that achieves maximum stability and minimum leakage over the design space. Increasing V/sub t/ with fin height and body thickness improves stability, decreases variability, and decreases source-drain leakage exponentially. But this necessitates the use of small t/sub ox/ to control short channel effect; this increases gate leakage exponentially. On the other hand, increasing V/sub t/ and decreasing V/sub dd/ allows the use of larger t/sub ox/ to maintain short-channel effect and control gate leakage; however, this worsens stability. Careful co-design of device structure, V/sub t/ and V/sub dd/ is imperative to optimize SRAM metrics.