Eliminating Inter-Thread Interference in Register File for SMT Processors

For simultaneous multithreaded (SMT) processors, a large rename register file (RRF) is indispensable for holding intermediate results of in-flight instructions from multiple threads. Meanwhile, inter-thread interferences lower the efficiency of RRF badly, exacerbating the pressure on RRF design. We propose Thread-Sensitive Register Renaming (TSRR), which tracks the performance variations and dynamically tunes the amount of rename registers available to each thread. In contrast to the traditional fullyshared RRF, this partly-shared scheme of TSRR guarantees (1) each thread has opportunities to fully exhibit its performance potential, (2) each thread can occupy just a reasonable number of rename registers, eliminating harmful inter-thread conflicts, and (3) the poorest-performance thread neither hinder other threads nor starve itself.