An imager with built-in image-velocity computation capability

An imager with built-in image-velocity computation capability is described. The image-velocity computation technique is based on signals propagating on delay lines. Silicon implementation using 3- mu m-CMOS technology is described. Experimental results show that a computational error of less than 20% can be achieved using available fabrication technology. This figure can be reduced by using larger arrays and better implementations of delay gates.<
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