A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters

In traditional comparators especially for flash ADCs, one serious problem is the kick back noise, which disturbs the input signal voltages and consequently might cause errors at the outputs of the ADCs. In this paper, we propose a novel CMOS latched comparator with very low kickback noise for high-speed flash ADCs. The proposed comparator separates analog preamplifier from the positive feedback digital dynamic latch so as to reduce the influence of the kickback noise. Simulation results based on a mixed signal CMOS 0.35 /spl mu/m technology show that, this comparator can work at a maximum clock frequency of 500 MHz with very reduced kickback noise compared with conventional architectures.