A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

A 20-Gb/s 256-Mb DRAM with the proposed PLL and transmitter schemes has been designed and fabricated using an 80-nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with cascaded pre-emphasis transmitter achieves 10-Gb/s/pin data rate.